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Logic-timing simulation and the degradation delay model / Manuel J. Bellido, Jorge Juan, Manuel Valencia
London : Imperial College Press, 2006
267tr. ; 24cm.
Bellido, Manuel J.
Contents: Fundamentals of Timing Simulation Delay Models: Evolution and Trends Degradation and Inertial Effects CMOS Inverter Degradation Delay Model Gate-Level DDM Logic Level Simulator Design and Implementation DDM Simulation Results Accurate Measurement of the Switching Activity
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